An innovative 11-level multilevel inverter topology with rotating trapezoidal SPWM for industrial and renewable applications (2024)

Multilevel inverters have become an essential component in modern power conversion systems, especially for industrial applications and renewable energy integration. These systems offer significant advantages, including lower harmonic distortion, reduced electromagnetic interference, and improved power quality¹. Among the various multilevel inverter topologies, cascaded H-bridge, diode-clamped, and flying capacitor inverters have been widely studied and applied. However, these conventional topologies face challenges such as increased complexity, high component count, and complex control strategies, which can limit their efficiency and reliability in large-scale applications^2,3,4. MLIs come in various configurations, each offering unique advantages and applications. Common types include diode-clamped (neutral-point clamped), cascaded H-bridge, flying capacitor, and hybrid multilevel inverters^5,6,7,8. Diode-clamped inverters utilize clamping diodes to create multiple voltage levels, while H-bridge inverters in cascade consist of multiple H-bridge units connected in series, offering scalability and high-voltage capability⁹. Flying capacitor inverters employ capacitors to generate voltage levels, and hybrid inverters combine features from different topologies to optimize performance¹⁰.

Multilevel inverters could be classified as symmetric or asymmetric according to the distribution of voltage levels. Symmetric multilevel inverters generate voltage levels evenly around a reference voltage, resulting in balanced operation¹¹. In contrast, asymmetric multilevel inverters produce voltage levels that are not symmetrically distributed, offering greater flexibility in voltage control and modulation. In multilevel inverters, pulse-width modulations techniques are utilized to maintain control the output voltage waveform¹². One such method is called sinusoidal Pulse Width Modulation (SPWM)¹³ where the width of the switching pulses is adjusted to approximate a sinusoidal waveform¹⁴. This method aims to minimize harmonic distortion by closely matching the modulation signal’s frequency with the desired output frequency. Space Vector PWM (SVPWM)^15,16,17,18 is another advanced technique that operates in a rotating reference frame. It synthesizes the output voltage using three adjacent voltage vectors, resulting in improved voltage utilization and reduced harmonic content compared to SPWM¹⁹.

Selective Harmonic Elimination PWM (SHE PWM)²⁰ is accustomed to selectively take out particular harmonics from the waveform of the output voltage with the aid of a series of nonlinear equations. By intelligently choosing switching angles, SHE PWM²¹ can achieve precise harmonic elimination while maintaining desired fundamental voltage levels. Carrier-Based PWM modulates the switching signals based on carrier waveforms, typically triangular or sawtooth waves, to generate the desired output voltage waveform²². This technique involves comparing the carrier wave with a reference waveform and generating the switching signals accordingly. Finally, Phase-Shifted PWM²³ involves shifting the phase angle of the carrier signals to control the output voltage magnitude and phase angle. By adjusting the phase shift between multiple carrier signals, this technique can achieve better utilization of voltage levels and reduced harmonic distortion. Each PWM²⁴ technique offers its own trade-offs in terms of complexity, harmonic performance, and efficiency, allowing for tailored solutions in multilevel inverter applications²⁵.

Despite the advances in multilevel inverter technology, a significant research gap remains in achieving a balance between reducing the number of power electronic components and maintaining high output quality. Traditional pulse width modulation (PWM)²⁶ techniques, such as sinusoidal PWM (SPWM)²⁷ and space vector PWM (SVPWM)²⁸, often struggle to minimize harmonic distortion without compromising on the simplicity of the control algorithm. This is particularly critical in renewable energy systems, where the inverter’s performance directly impacts the overall system efficiency and power quality²⁹. To address these challenges, this paper proposes an innovative 11-level multilevel inverter topology that leverages a Rotating Trapezoidal SPWM (RT-SPWM) technique. The topology aims to reduce the number of switches and associated components while maintaining high output quality with lower total harmonic distortion (THD). This makes it particularly suitable for industrial and renewable energy applications, where efficiency, reliability, and compactness are paramount^30,31,32. Applications requiring low to medium voltage can make use of the proposed technology. The voltage ratings in distribution generation systems, such as grid integration with small-scale solar PV, will fall into the middle ranges^33,34. The following attributes of the suggested topology,

• For an 11-level inverter, it has eight switches.

• It has 3 DC sources.

• It works with all kinds of loads.

• The efficiency is increased and switching losses are reduced when four switches run at fundamental frequency.

• Advanced sawtooth carrier- and triangular carrier-based multi-carrier sinusoidal pulse width modulation, Rotating Trapezoidal Sinusoidal Pulse Width modulation is employed in order to regulate the proposed MLI switching sequence.

• Optimized switching sequence achieved by regulating the load on the switch. The below Table1 shows the number of components used in the proposed multilevel inverter is less when compared to all topologies mentioned in the list of tables.

By utilizing three dc voltage sources, the suggested³⁷ rudimentary unit can achieve eleven levels at the result. The rudimentary unit can be increased to generate an increased quantity of levels. This augmentation increases the quantity of bidirectional switches various sources of DC voltage³⁸. That is attached to the module’s interior. There are three cells that can be formed from the switches within the suggested topology. Switches \(\,{S}_{1}\) and \(\,{S}_{2}\) comprise Cell 1. Cell 1, switches run at fundamental frequency since each³⁹ of them must withstand the highest possible voltage stress. Cell 2 comprises all among the internal switches, and during a half cycle, each switch can be turned ON for any two levels⁴⁰. Similar to cell 2, cell 3 consists of two high-frequency switches, \(\,{S}_{5}\) and \(\,{S}_{6}\) . The half-cycle depiction of the 11-level inverter with five positive voltage levels \(\,{V}_{1,\,}{V}_{2},\,{V}_{1}{+V}_{2},\,2{V}_{2},\,{V}_{1}+2{V}_{2}\) is depicted in Fig.1⁴¹. Switches \(\,{S}_{1\,}\) & \(\,{\,S}_{3}\) are in conduction mode at voltage level \(\,{V}_{1\,},\) switches \(\,{\,S}_{1}\), \(\,{S}_{5}\) & \(\,{S}_{11}\) are in conduction mode at voltage level \(\,{V}_{2}\), switches \(\,{S}_{1\,}\) & \(\,{\,S}_{11}\) are in conduction mode at voltage level \(\,{V}_{1}{+V}_{2}\), switches \(\,{S}_{1}\), \(\,{S}_{4\,}\&{\,S}_{5}\) are in conduction mode at voltage level \(\,2{V}_{2}\), and switches \(\,{S}_{1}\&{S}_{4}\) are in conduction mode at voltage levels \(\,{V}_{1}+2{V}_{2\,}\) respectively⁴².

Regarding the suggested structure utilizing k dc voltage sources, the generalized equations are in as follows:

K = number of DC voltage sources used in the circuit = 3

V₁ = V_dc Substitute in (3) then.

N = number of levels, \(\,{V}_{\text{d}\text{c}}=\text{i}\text{n}\text{p}\text{u}\text{t}\,\text{d}\text{c}\,\text{v}\text{o}\text{l}\text{t}\text{a}\text{g}\text{e}\,\text{s}\text{o}\text{u}\text{r}\text{c}\text{e}\)

Another method of increasing the number of levels at the output is to cascade many modules. The cascade connection of the suggested topology⁴³ with m modules is depicted in Fig.2. The total voltage produced by all the modules connected in cascade is the output voltage across the load⁴⁴.

Figure3 illustrates the fundamental component of the proposed multilevel inverter topology. There are six unidirectional and one bidirectional switch. Make up the assembly, which also includes three dc voltage sources⁴⁵. External switches are switch pairs \(\,{(\,S}_{1}\), \(\,{\,S}_{2})\) and \(\,{\,(S}_{5}\), \(\,{\,S}_{6})\) and each pair requires only one switch to be activated. In order to prevent shorting out the DC voltage sources, the outer pair’s switches ought to likewise function in a move that is complementary⁴⁶. These external switches are wired in series with voltage source \(\,{\,V}_{1}\) . The interior of the suggested fundamental unit is formed by the two remaining DC voltage sources that have magnitude \(\,{\,V}_{2}\), consist of the bidirectional switch \(\,{\,S}_{11}\), the unidirectional switches \(\,{\,S}_{3}\), and the switches \(\,{\,S}_{4}\), all connected in series with additive polarity⁴⁷. Between these three switches, only one switch needs to be turned on. In light of these details, Table2 presents the suggested basic unit’s switching table.

Mode-1(\({\varvec{V}}_{1}\))

In this mode \(\,{\,S}_{1}\), \(\,{\,S}_{3}\) and \(\,{\,S}_{6}\) are activated, and the other switches are in the off position. The voltage source \(\,{V}_{1}\) is connected in succession with switches \(\,{\,S}_{1}\) and \(\,{\,S}_{6}\) . Thus, as a result of these switches being connected in series, voltage level \(\,{V}_{1}\) appears across the load. The mode 1 equivalent connection is shown in Fig.4(a).

Mode-2(\({\varvec{V}}_{2}\))

In this mode \(\,{\,S}_{1}\), \(\,{\,S}_{5},{\,S}_{11}\) are activated, as well as the additional switches being in off position. The voltage source \(\,{\,V}_{2\,}\) is connected in series with switches \(\,{\,S}_{1}\) and \(\,{\,S}_{5}\) . Thus, as a result of these switches being connected in series, voltage level \(\,{\,V}_{2}\) appears across the load. The mode 2 equivalent connection is shown in Fig.4(a).

Mode-3(\({\varvec{V}}_{1}+{\varvec{V}}_{2}\))

In this mode \(\,{\,S}_{1}\), \(\,{\,S}_{6}\) are activated, as well as the additional switches being in off position. The voltage source \(\,\left({V}_{1}+{V}_{2}\right)\) is connected in series with switches \(\,{\,S}_{1}\) and \(\,{\,S}_{6}\) . Thus, as a result of these switches being connected in series, voltage level \(\,\left({V}_{1}+{V}_{2}\right)\) appears across the load. The mode 3 equivalent connection is shown in Fig.4(a).

Mode-4(2 \({\varvec{V}}_{2}\))

In this mode \(\,{\,\,S}_{1}\), \(\,{\,\,S}_{4},\,{\,S}_{5}\) are activated, and the other switches are in the off position. The voltage source \(\,{\,2\, V}_{2\,}\) is connected in series with switches \(\,{\,S}_{1}\), \(\,{\,S}_{4}\) and \(\,{\,S}_{5}\) . Thus, as a result of these switches being connected in series, voltage level \(\,{\,2\, V}_{2\,}\) appears across the load. The mode 4 equivalent connection is shown in Fig.4(a).

Mode-5(\({\varvec{V}}_{1}+2{\varvec{V}}_{2}\))

In this mode \(\,{\,\,S}_{1}\), \(\,{\,\,S}_{4},{\,S}_{6}\) are activated, and the other switches are in the off position. The voltage source \(\,{V}_{1}+2{V}_{2}\) is connected in series with switches \(\,{\,\,S}_{1}\), \(\,{S}_{4}\) and \(\,{\,\,S}_{6}\) . Thus, as a result of these switches being connected in series, voltage level \(\,{V}_{1}+2{V}_{2}\) appears across the load. The mode 5 equivalent connection is shown in Fig.4(a).

Mode-6(0 V)

In this mode \(\,{\,\,S}_{2}\), \(\,{\,\,S}_{4},{\,S}_{6}\) are activated, and the other switches are in the off position. Upon connecting these switches, a voltage level of 0 V is observed across the load. The mode 6 equivalent connection is shown in Fig.4(a).

Mode-7(- \({\varvec{V}}_{1}\))

In this mode \(\,{\,\,S}_{2}\), \(\,{\,\,S}_{4},{S}_{5}\) are activated, and the other switches are in the off position. The voltage source \(\,-{V}_{1}\) is connected in succession with switches \(\,{\,\,S}_{2}\) and \(\,{\,\,S}_{5}\) . Thus, as a result of these switches being connected in series, voltage level \(\,-{V}_{1}\) appears across the load. The mode 7 equivalent connection is shown in Fig.4(b).

Mode-8(- \({\varvec{V}}_{2}\))

In this mode \(\,{\,\,S}_{2}\), \(\,{\,\,S}_{11},{S}_{6}\) are activated, as well as the additional switches being in off position. The voltage source \(\,-{V}_{2}\) is connected in series with switches \(\,{\,\,S}_{2}\) and \(\,{\,\,S}_{6}\) . Thus, as a result of these switches being connected in series, voltage level \(\,-{V}_{2}\) appears across the load. The mode 8 equivalent connection is shown in Fig.4(b).

Mode-9 -(\({\varvec{V}}_{1}+{\varvec{V}}_{2}\))

In this mode \(\,{\,\,S}_{2,}{\,S}_{5}\), \(\,{\,S}_{11}\) are activated, as well as the additional switches being in off position. The voltage source \(\,-\left({V}_{1}+{V}_{2}\right)\) is connected in series with switches \(\,{\,\,S}_{2}\) and \(\,{\,\,S}_{5}\) . Thus, as a result of these switches being connected in series, voltage level \(\,-\left({V}_{1}+{V}_{2}\right)\) appears across the load. The mode 9 equivalent connection is shown in Fig.4(b).

Mode-10 -(2 \({\varvec{V}}_{2}\))

In this mode \(\,{\,\,S}_{2,}\), \(\,{\,S}_{3,}{\,S}_{6}\) are activated, and the other switches are in the off position. The voltage source \(\,-\left(2{V}_{2}\right)\) is connected in series with switches \(\,{\,\,S}_{2,}{\,\,S}_{3}\) and \(\,{\,\,S}_{6}\) . Thus, as a result of these switches being connected in series, voltage level \(\,-\left(2{V}_{2}\right)\) appears across the load. The mode 10 equivalent connection is shown in Fig.4(b).

Mode-11-(\({\varvec{V}}_{1}+2{\varvec{V}}_{2}\))

In this mode \(\,{\,\,S}_{2,}\), \(\,{\,S}_{3,}{S}_{5,}\) are activated, and the other switches are in the off position. The voltage source \(\,-\left({V}_{1}+2{V}_{2}\right)\) is connected in series with switches \(\,{\,\,S}_{2,}{\,\,S}_{3,}\) and \(\,{\,\,S}_{5}\) . Thus, as a result of these switches being connected in series, voltage level \(\,-\left({V}_{1}+2{V}_{2}\right)\) appears across the load. The mode 11 equivalent connection is shown in Fig.4(b).

Calculation of total standing voltage (TSV)

On the basis of the operating modes displayed in Fig.2, the TSV can be assessed^{48,49,50,51,52}. The blocking voltage of switches is used to calculate their maximum voltage blocking capability.

Across the bidirectional switches, the voltage stress is

Where \(\,i=\text{1,2},\dots\,.\text{n}\)

The representation of the stress across each individual switch is as follows.

TSV is calculated as

The voltage stress across each switch in detail with percentages is shown in below Table3.

It is necessary to compute the current flowing through the switches while they are in the on state to be able to assess power losses and choose the switches. If the multilevel inverter is designed with a large number of levels, then the output current waveform can be assumed to be sinusoidal⁵³. Average current can be computed by,

Only in the first quarter of the time frame is the average current multiplied by two due to the signal symmetry⁵⁴. \(\,{I}_{m}\) ’s value can be ascertained by

Were, \(\,{R}_{L}=\,\) Resistance of the load, \(\,{X}_{L}=\,\) Reactance of the load, and \(\,{{V}_{0}}_{max}=\,\) Peak of output voltage with respect to the output RMS current, Fig.5 displays the switches’ current rating normalized⁵⁵.

All of the switches’ RMS current

As illustrated in Fig.5, the RMS was computed and normalized for each switch, just like the average current. Since each switch has a distinct rating, the average current rating for each switch from \(\,{S}_{1}\) to \(\,{S}_{11}\) is 12.14%, 12.14%, 43.83%, 43.83%, 32.74%, 32.74%, 44.88% meanwhile the RMS current rating of each switch is 15.63%, 15.63%, 50.26%, 50.26%, 43.45%, 43.45%, 50% as shown in the bar graph in Fig.5. It is possible to choose the switch based on these parameters to maximize thermal design, power rating, and cost⁵⁶.

Conduction losses

Utilizing the on-voltage drop of the switch, conduction losses can be determined as⁵⁷

\(\,{V}_{on}\left(t\right)=\,\) Conduction voltage drop

\(\,i\left(t\right)=\) Current passing across the switch

\(\,{r}_{ON}=\,\) ON resistance

Overall conducting losses come to

\(\,{V}_{T}=\,\) Saturation voltage

\(\,{R}_{T}=\,\) Conduction resistance

\(\,{V}_{D}=\,\) Drop in forward voltage

\(\,{R}_{D}=\,\) Single diode on resistance

The Fig.6(a) depicts the Conduction losses for each switch.

Switching losses

The energy lost during the transition⁵⁸ multiplied by the frequency of switching is what determines the switching losses. Energy losses in both the on and off transitions.

\(\,{t}_{on}=\) Duration of on state transition

\(\,{t}_{off}=\,\) Duration of off state transition

\(\,{v}_{\left(t\right)}=\) Voltage during switching transition

\(\,{i}_{\left(t\right)}=\,\) Current during switching transition

I = current passes via the switch, both in the start as well as the off-transition finish of the on-transition and \(\,{V}_{switch}=\,\) Voltage passes through the switch, both at the start of the off-transition and the finish of the on-transition⁵⁹. The overall switching losses come to

The Fig.6(b) depicts the Switching losses for each switch, and the efficiency can be computed as follows using conducting and switching losses⁶⁰.

Consider \(\,\varDelta\,t=1\text{\,}\mu\,s\), \(\,T=20\text{\,ms}\) and \(\,{V}_{T}+2{V}_{D}=3.5\text{\,V},\,{R}_{T}+2{R}_{D}=90\text{\,m}\varOmega\,\,\) for instance, \(\,{E}_{1}=50\text{\,V}\) which denotes a maximum output voltage of 250 V and I_m = 100 A, has a maximum efficiency of 99% and pre dominates conduction losses. Upgrades to the switches may result in even greater efficiency.

A variety of open- and closed-loop techniques and algorithms are typically used to control multilevel inverters⁶¹. Proposed 11-level MLI topology is controlled using various advanced triangular carrier-based sinusoidal pulse width modulation (SPWM) techniques in open-loop methods. The following describes how carrier-based advanced SPWM techniques are used⁶². The Proposed 11-level MLI only takes into account the 10 triangular multi-carriers (number of carriers = number of levels − 1) each triangular carrier has two bare minimum spots at the carrier’s starting and finishing points and one maximum position at its midpoint⁶³. The model Wave forms of different pulse width modulation techniques are shown in Figs.7 and 8.

Phase disposition SPWM technique

The ten carriers in the PD-SPWM method are all the same as shown in Fig.7(a); they all function at the identical frequency of switching, with equal displacements for amplitude and phase⁶⁴, and the triangular carrier arrangement keeps the carriers at two levels. Minimum numbers of places and one top-level role exclusively in the center of the carrier⁶⁵.

Phase opposition disposition SPWM technique

Although carrier establishment differs, this method is identical to PD-SPWM as shown in Fig.7(b). Based on positive or negative average levels, the carriers are evenly split into two groups. In this⁶⁶ kind of grouping, the two groups are out of phase with one another but still in phase with the group as a whole. When using POD-SPWM modulation, every carrier waveform above the 0 point of reference is within a phase, yet, those beneath the reference zero is out of phase by 180 degrees. Every carrier wave that is above zero is in phase, whereas every wave below zero is 180° out of phase. When the number of levels is m = 11. Similarly, for \(\,\left(m-1\right)\) = 10carrier waveforms are arranged.

Alternative phase opposition disposition SPWM technique

An APOD-SPWM modulation’s carrier waves are all 180 degrees out of phase⁶⁷ with its neighboring carrier as shown in Fig.7(c). An eleven-level inverter is taken into consideration when discussing the APOD-SPWM scheme because, when dealing with a three-level inverter, the APOD-SPWM and POD-SPWM schemes are identical⁶⁸. The arrangement of carrier waveforms ensures that every carrier is 180 degrees out of sync with the adjacent carrier when the number of levels is m = 11. This equals m – 1 = 10 adjacent bands’ carriers have a \(\,{180}^{\circ}\) phase shift. The most significant harmonics are centred as auxiliary bands around the carrier when employing this strategy⁶⁹.

IN-shift SPWM technique

The ten carriers in the IN-Shift SPWM method are all the out of phase⁷⁰; they all function at the identical switching frequency, with unequal displacements for amplitude and phase as shown in Fig.7(d), and the triangular carrier arrangement keeps the carriers at two levels. Minimum numbers of places and one top-level role exclusively in the center of the carrier⁷¹.

Rotating trapezoidal SPWM technique

The ten Trapezoidal signals in the rotating trapezoidal SPWM method are all the same; they all function at the identical switching frequency, with equal displacements for amplitude and phase^72,73,74.

Peak voltage \(\,\left({V}_{p}\right)\) = 250 V for 11-level Voltages

One Half-Cycle Contains 11 Time periods

A single pulse width time frame

Eleven distinct firing angles are present in a half-cycle

A single firing angle for a single pulse width

Six distinct modes, which are described in detail in Table2, are depicted as the current path in Fig.2. To prevent a short circuit in the inputs, the switches must be turned on and off. Figure2; Table4 illustrate the transition angles, \(\,{\propto\,}_{1},\,{\propto\,}_{2},\,{\propto\,}_{3},\,{\propto\,}_{4},\,{\propto\,}_{5}\) at which the change from one state to the next occurs. The converter uses the 11 levels to modify its output 20 times in a whole cycle, which lasts 20ms (50Hz).

Logic diagram of rotating trapezoidal SPWM technique

The control diagram for the new rotating trapezoidal SPWM approach is depicted in Fig.9. It uses ten carrier waves to produce pulses with the corresponding signs \(\,{X}_{1},\,{X}_{2},\,{X}_{3},\,{X}_{4},\,{X}_{5},\,{X}_{6},\,{X}_{7},\,{X}_{8},\,{X}_{9},\,{X}_{10}\) . After comparing the pulses to the reference signal, the switches are given the appropriate logic to produce the 11-level output voltage. This procedure will be repeated for various modulation indices of 0.2, 0.4, 0.6, 0.8, and 1.0 in order to assess the inverter’s performance.

Regulating demonstration of the 11-level MLI is confirmed regarding overall harmonic analysis, by means of a PD-SPWM controller based on a triangle carrier and an RL load at a modulation index (MI) of 1.0M. In comparison to other modulations of 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, and 0.9, Fig.9 shows the voltage and current waveforms of 11-level inverter with PD-SPWM technique, it produces fewer harmonics at modulation index 1.0 (11.38%, 6.86%) is the load voltage and load current THD values, as shown in Fig.10.

Regulating demonstration of the 11-level MLI is confirmed regarding overall harmonic analysis, by means of a POD-SPWM controller based on a triangle carrier and an RL load at a modulation index (MI) of 1.0M. In comparison to other modulations of 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, and 0.9, Fig.10 shows the voltage and current waveforms of 11-level inverter with POD-SPWM technique, it produces fewer harmonics at modulation index 1.0 (6.43%, 2.27%) is the load voltage and load current THD values, as shown in Fig.11. The regulating performance of the 11-level MLI is regarding overall harmonic analysis, by means of an APOD-SPWM controller based on a triangle carrier and an RL load at a modulation index (MI) of 1.0M. In comparison to other modulations of 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, and 0.9, Fig.11 shows the voltage and current waveforms of 11-level inverter with APOD-SPWM technique, it produces fewer harmonics at modulation index 1.0 (6.69%, 2.81%) is the load voltage and load current THD values, as shown in Fig.12. The regulating performance of the 11-level MLI is confirmed regarding overall harmonic analysis, by means of an IN-Shift-SPWM controller based on a triangle carrier and an RL load at a modulation index (MI) of 1.0M. In comparison to other modulations of 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, and 0.9, Fig.12 shows the voltage and current waveforms of 11-level inverter with IN Shift SPWM technique, it produces fewer harmonics at modulation index 1.0 (3.93%, 1.64%) is the load voltage and load current THD values, as shown in Fig.13.

Using a Rotating Trapezoidal SPWM controller at a modulation index (MI) of 1.0M with an RL load, the masterful execution of the 11-level MLI is confirmed regarding the whole harmonic analysis. In comparison to other modulations of 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, and 0.9, Fig.13 shows the voltage and current waveforms of 11-level inverter with Rotating Trapezoidal SPWM technique, it produces fewer harmonics at modulation index 1.0 (3.45%, 1.60%) is the load voltage and load current THD values, as shown in Fig.14.

PWM approaches’ overall performances were examined for different frequency’s using Tables5 and 6 and, The THD of the PD-SPWM method is 11.38% and 6.86% at MI = 1; 14.65% and 7.01% at MI = 0.8; 15.54% and 8.14% at MI = 0.6; 20.08% and 10.57% at MI = 0.4; 21.28% and 14.45% at MI = 0.2 for load voltage and load currents respectively. The THD of the POD-SPWM method is 6.43% and 2.27% at MI = 1; 12.24% and 4.71% at MI = 0.8; 17.21% and 7.69% at MI = 0.6; 15.27% and 6.61% at MI = 0.4; 23.12% and 12.52% at MI = 0.2 for load voltage and load currents respectively. The THD of the APOD-SPWM method is 6.69% and 2.81% at MI = 1; 13.71% and 5.25% at MI = 0.8; 16.17% and 7.51% at MI = 0.6; 19.32% and 9.14% at MI = 0.4; 22.05% and 11.51% at MI = 0.2; for load voltage and load currents respectively. The THD of the IN-Shift-SPWM method is 3.93% and 1.64% at MI = 1; 11.07% and 3.82% at MI = 0.8; 14.10% and 5.61% at MI = 0.6; 17.45% and 7.28% at MI = 0.4; 20.24% and 9.05% at MI = 0.2; for load voltage and load currents respectively. The THD of the Rotating Trapezoidal SPWM is 3.45% and 1.60% at MI = 1; 10.51% and 3.03% at MI = 0.8; 13.14% and 4.98% at MI = 0.6; 16.24% and 6.17% at MI = 0.4; 19.08% and 8.04% at MI = 0.2; for load voltage and load currents respectively. The simulation parameters used is discussed in Table7.

Figure15 shows the prototype of a single-phase, 11-level, multilevel inverter with a 24 V output voltage, which was used to perform the modulation methods outlined in Sect.7 in real time. In the Digital Signal Controller (DSC) dSPIC20F2010, the modulation approach is applied. MOSFET switches comprise a single module that makes up the experimental setup. A DSP and microcontroller are combined to form a DSC. Both microcontroller and DSP features are present in it. With DSC, analog signals are measured, filtered, and compressed more quickly. With high-performance 16-bit microcontroller architecture, Microchip has produced devices, the dsPIC30F, that have significant DSP functionality. Six PWM output channels, three 16-bit timers/counters, four 16-bit capture input functions, dual data fetch, and a modified Harvard architecture are among the features of the dsPIC30F2010. Table8 displays the specifications for each of these characteristics.

The modulation schemes are implemented by DSC dsPIC30F2010. For code generation and compilation Microchip Technology’s Integrated Development Environment (MPLAB)⁷⁵ software is being used for the DSC. This DSC has three 16 bit timers/counters. Figure16 shows the THD obtained from the hardware prototype. Figures10, 11, 12, 13, 14 and 16 (a-e) shows the THD analysis of the output voltage in MATLAB and experimental. The figures indicate that the modulation schemes generate similar voltages. The differences in the output of the modulation schemes can be easily distinguished in terms of output voltage THD as shown in Table9.